Synopsys Hiring Fresher Software Application Engineer 2024 | Bachelor’s or Master’s degree
"We are currently looking for a dynamic and skilled
Software Application Engineer with a strong background in hierarchical flow
knowledge and a proven track record in diverse top-level implementation
processes."
ELIGIBILITY CRITERIA FORSYNOPSYS SOFTWARE
APPLICATION ENGINEER 2024
Synopsys Hiring Fresher Software Application Engineer 2024
Job Designation :
Software Application Engineer
Qualification :
Bachelor’s or Master’s degree
Experience :
Freshers
Location :
Hyderabad, Telangana, India
ROLES & RESPONSIBILITIES
The Applications Engineer role at Synopsys presents a unique opportunity to tackle the most demanding technical challenges in the verification domain and cutting-edge technologies within the Synopsys Verification Platform. We are looking for a motivated, fresh individual who enjoys problem-solving, values continuous learning, is passionate about working with advanced technologies, and has excellent communication skills. This role provides exposure to a wide range of HDL/HVL, methodologies, static and formal verification, dynamic simulation, debugging, and experience working in a diverse environment with domain experts across global locations.
·
Develop and implement hierarchical flow
methodologies for intricate ASIC designs.
·
Collaborate closely with cross-functional
teams including architects, RTL designers, physical designers, and verification
teams to ensure high-quality and timely delivery of design products.
·
Analyze timing reports and collaborate with
design teams to address timing issues.
·
Optimize designs for power, performance, and
area.
·
Conduct floor planning and place-and-route of
top-level modules.
·
Participate in the development of new design
methodologies and flows to enhance design quality, efficiency, and
time-to-market.
Location : Hyderabad, Telangana, India
SKILLS REQUIRED FOR Software Application Engineer 2024
·
Must have strong foundational knowledge in
Digital design, HDLs (Verilog/VHDL), and System Verilog.
·
Should possess a solid understanding of
hierarchical design methodologies.
·
Must be proficient in UNIX, Tcl, and/or other
scripting languages to effectively execute tasks.
·
Experience with dynamic simulation
verification, including System Verilog, Verilog, methodologies, debug, low
power, and coverage, is beneficial.
·
Exposure to Synopsys EDA tools (VCS, Verdi)
would be an added advantage.
·
A team player who collaborates with multiple
stakeholders, pays attention to detail, and fosters an innovative mindset.
·
Must be motivated, proactive, and
well-organized, with good interpersonal communication skills.
·
Open to travel, can manage multiple tasks
simultaneously, and has a keen eye for detail.
·
Excellent written and verbal communication
skills are essential, as the role involves interfacing with clients,
understanding their challenges, and proposing solutions.